ARM Ltd. Musca 2025.07.02 ARM 32-bit v8-M Mainline based device CM33 r0p1 little true 3 false 8 32 CODE_SRAM_MPC Code SRAM Memory Protection Controller SRAM_MPC 0x50130000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF DUALTIMER Dual Timer Timer 0x40002000 0x0 0x3C registers n DUALTIMER Dual Timer 5 TIMER1BGLOAD Timer 1 Background Load Register 0x18 read-write n 0x0 0xFFFFFFFF TIMER1CONTROL Timer 1 Control Register 0x8 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER1LOAD Timer 1 Load Register 0x0 read-write n 0x0 0xFFFFFFFF TIMER1MIS Timer 1 Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER1RIS Timer 1 Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER1VALUE Timer 1 Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF TIMER2BGLOAD Timer 2 Background Load Register 0x38 read-write n 0x0 0xFFFFFFFF TIMER2CONTROL Timer 2 Control Register 0x28 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x2C write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER2LOAD Timer 2 Load Register 0x20 read-write n 0x0 0xFFFFFFFF TIMER2MIS Timer 2 Mask Interrupt Status Register 0x34 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER2RIS Timer 2 Raw Interrupt Status Register 0x30 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER2VALUE Timer 2 Value Register 0x24 read-only n 0xFFFFFFFF 0xFFFFFFFF DUALTIMER_Secure Dual Timer (Secure) Timer 0x50002000 0x0 0x3C registers n TIMER1BGLOAD Timer 1 Background Load Register 0x18 read-write n 0x0 0xFFFFFFFF TIMER1CONTROL Timer 1 Control Register 0x8 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER1LOAD Timer 1 Load Register 0x0 read-write n 0x0 0xFFFFFFFF TIMER1MIS Timer 1 Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER1RIS Timer 1 Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER1VALUE Timer 1 Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF TIMER2BGLOAD Timer 2 Background Load Register 0x38 read-write n 0x0 0xFFFFFFFF TIMER2CONTROL Timer 2 Control Register 0x28 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x2C write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER2LOAD Timer 2 Load Register 0x20 read-write n 0x0 0xFFFFFFFF TIMER2MIS Timer 2 Mask Interrupt Status Register 0x34 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER2RIS Timer 2 Raw Interrupt Status Register 0x30 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER2VALUE Timer 2 Value Register 0x24 read-only n 0xFFFFFFFF 0xFFFFFFFF GPIO0 General-purpose I/O 0 GPIO 0x40110000 0x0 0x3C registers n GPIO0 GPIO 0 combined 68 ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPIO0_Secure General-purpose I/O 0 (Secure) GPIO 0x50110000 0x0 0x3C registers n ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPTIMER General-Purpose Timer Timer 0x4010B000 0x0 0x20 registers n GPTIMERINT1 General-Purpose Timer (Comparator 1) 72 GPTALARM0 ALARM0 data value register 0x10 read-write n 0x0 0xFFFFFFFF GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM1 ALARM1 data value register 0x14 read-write n 0x0 0xFFFFFFFF GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTCOUNTER Counter data value register 0x1C read-only n 0x0 0xFFFFFFFF GPTCOUNTER Current value of 32-bit Timer Counter 0 32 GPTINTC Interrupt clear register 0x8 read-write n 0x0 0xFFFFFFFF GPTINTC Writing 0b1 disables the ALARM[n] interrupt 0 2 Reserved Reserved 2 32 GPTINTM Masked interrupt status register 0x4 read-write n 0x0 0xFFFFFFFF GPTINTM Current masked status of the interrupt 0 2 Reserved Reserved 2 32 GPTINTR Raw interrupt status register 0x18 read-only n 0x0 0xFFFFFFFF GPTINTR Raw interrupt state, before masking of GPTINTR interrupt 0 3 Reserved Reserved 3 32 GPTRESET Control Reset Register 0x0 read-only n 0x0 0xFFFFFFFF GPTRESET CPU0 interrupt status 0 2 Reserved Reserved 2 32 GPTIMER_Secure General-Purpose Timer (Secure) Timer 0x5010B000 0x0 0x20 registers n GPTALARM0 ALARM0 data value register 0x10 read-write n 0x0 0xFFFFFFFF GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM1 ALARM1 data value register 0x14 read-write n 0x0 0xFFFFFFFF GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTCOUNTER Counter data value register 0x1C read-only n 0x0 0xFFFFFFFF GPTCOUNTER Current value of 32-bit Timer Counter 0 32 GPTINTC Interrupt clear register 0x8 read-write n 0x0 0xFFFFFFFF GPTINTC Writing 0b1 disables the ALARM[n] interrupt 0 2 Reserved Reserved 2 32 GPTINTM Masked interrupt status register 0x4 read-write n 0x0 0xFFFFFFFF GPTINTM Current masked status of the interrupt 0 2 Reserved Reserved 2 32 GPTINTR Raw interrupt status register 0x18 read-only n 0x0 0xFFFFFFFF GPTINTR Raw interrupt state, before masking of GPTINTR interrupt 0 3 Reserved Reserved 3 32 GPTRESET Control Reset Register 0x0 read-only n 0x0 0xFFFFFFFF GPTRESET CPU0 interrupt status 0 2 Reserved Reserved 2 32 NSPCTRL Non-secure Privilege Control Block NSPCTRL 0x40080000 0x0 0x1000 registers n AHBNSPPPC0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control #0 0x90 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC 32 read-write n 0x0 0xFFFFFFFF APBNSPPPC0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 32 read-write n 0x0 0xFFFFFFFF APBNSPPPC1 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC 32 read-write n 0x0 0xFFFFFFFF CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x53 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x0 0xFFFFFFFF QSPIFCTRL QSPI Flash Controller QSPI 0x4010A000 0x0 0xB0 registers n QSPIINTR QSPI interrupt 38 DEVREADINSTR Device Read Instruction Register 0x4 read-write n 0x3 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 DDRBITEN DDR Bit Enable 10 11 INSTRTYPE Instruction Type 8 10 MODEBITEN Mode Bit Enable 20 21 READDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Read Instruction 24 29 Reserved Reserved 11 12 Reserved Reserved 21 24 Reserved Reserved 18 20 Reserved Reserved 14 16 Reserved Reserved 14 16 ROPCODE Read Opcode to use when not in XIP mode 0 8 DEVSIZE Device Size Configuration Register 0x14 read-write n 0x101002 0xFFFFFFFF ADDRBYTENUM Number of address bytes 0 4 BYTEPERBLKNUM Number of bytes per block 16 21 BYTEPERDEVPGNUM Number of bytes per device page 4 16 FDEVSIZECS0 Size of Flash Device connected to CS[0] pin 21 23 FDEVSIZECS1 Size of Flash Device connected to CS[1] pin 23 25 FDEVSIZECS2 Size of Flash Device connected to CS[2] pin 25 27 FDEVSIZECS3 Size of Flash Device connected to CS[3] pin 27 29 Reserved Reserved 29 32 DEVWRITEINSTR Device Write Instruction Configuration Register 0x8 read-write n 0x2 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 Reserved Reserved 9 12 Reserved Reserved 18 24 Reserved Reserved 14 16 Reserved Reserved 14 16 WELDISABLE WEL Disable 8 9 WRITEDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Write Instruction 24 29 WROPCODE Write Opcode 0 8 FLASHCMDADDR Flash Command Address Register 0x94 read-write n 0x0 0xFFFFFFFF FLASHCMDCTRL Flash Command Control Register 0x90 read-write n 0x0 0xFFFFFFFF ADDRBYTENUM Number of Address Bytes 16 18 CMDADDREN Command Address Enable 19 20 CMDEXEC Execute the command 0 1 CMDEXINPROG Command execution in progress 1 2 CMDOPCODE Command Opcode 24 32 DUMCYCNUM Number of Dummy Cycles 7 12 MODEBITEN Mode Bit Enable 18 19 RDATABYTENUM Number of Read Data Bytes 20 23 RDATAEN Read Data Enable 23 24 Reserved Reserved 2 7 WRDATABYTENUM Number of Write Data Bytes 12 15 WRDATAEN Write Data Enable 15 16 FLASHCMDRDATALOW Flash Command Read Data Register (Lower) 0xA0 read-only n 0x0 0xFFFFFFFF FLASHCMDRDATAUP Flash Command Read Data Register (Upper) 0xA4 read-only n 0x0 0xFFFFFFFF FLASHCMDWRDATALOW Flash Command Write Data Register (Lower) 0xA8 read-write n 0x0 0xFFFFFFFF FLASHCMDWRDATAUP Flash Command Write Data Register (Upper) 0xAC read-write n 0x0 0xFFFFFFFF QSPICFG QSPI Configuration Register 0x0 read-write n 0x80780081 0xFFFFFFFF AHBDECEN Enable AHB Decoder 23 24 CLKPHASE Clock phase, this maps to the standard SPI CPHA transfer format 2 3 CLKPOLARITY Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format 1 2 DTREN Enable DTR Protocol 24 25 ENAHBADDRRM Enable AHB Address Re-mapping 16 17 ENDIRACCCTR Enable Direct Access Controller 7 8 ENDMAPIF Enable DMA Peripheral Interface 15 16 ENTRXIPMODEIMM Enter XIP Mode immediately 18 19 ENTRXIPMODEONR Enter XIP Mode on next READ 17 18 LEGIPMODEEN Legacy IP Mode Enable 8 9 MAMOBRDIV Master mode baud rate divisor (2 to 32) 19 23 PERCSLINES Peripheral chip select lines 10 14 ss3 n_ss_out: 0b0111 0b0111 ssinactive n_ss_out: 0b1111 (no peripheral selected) 0b1111 ss2 n_ss_out: 0b1011 0bx011 ss1 n_ss_out: 0b1101 0bxx01 ss0 n_ss_out: 0b1110 0bxxx0 PERSELDEC Peripheral select decode 9 10 Disabled Only 1 of 4 selects n_ss_out is active 0 Enabled Allow external 4-to-16 decode 1 PHYMODEEN PHY Mode enable 3 4 PIPLIDLE Serial Interface and QSPI pipeline is IDLE 31 32 PIPLPHYEN Pipeline PHY Mode enable 25 26 QSPIEN QSPI Enable 0 1 Reserved Reserved 4 7 Reserved Reserved 26 31 WPPINDRV Set to drive the WP pin of Flash device 14 15 REMAPADDR Remap Address Register 0x24 read-write n 0x0 0xFFFFFFFF QSPIFCTRL_Secure QSPI Flash Controller (Secure) QSPI 0x5010A000 0x0 0xB0 registers n DEVREADINSTR Device Read Instruction Register 0x4 read-write n 0x3 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 DDRBITEN DDR Bit Enable 10 11 INSTRTYPE Instruction Type 8 10 MODEBITEN Mode Bit Enable 20 21 READDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Read Instruction 24 29 Reserved Reserved 11 12 Reserved Reserved 21 24 Reserved Reserved 18 20 Reserved Reserved 14 16 Reserved Reserved 14 16 ROPCODE Read Opcode to use when not in XIP mode 0 8 DEVSIZE Device Size Configuration Register 0x14 read-write n 0x101002 0xFFFFFFFF ADDRBYTENUM Number of address bytes 0 4 BYTEPERBLKNUM Number of bytes per block 16 21 BYTEPERDEVPGNUM Number of bytes per device page 4 16 FDEVSIZECS0 Size of Flash Device connected to CS[0] pin 21 23 FDEVSIZECS1 Size of Flash Device connected to CS[1] pin 23 25 FDEVSIZECS2 Size of Flash Device connected to CS[2] pin 25 27 FDEVSIZECS3 Size of Flash Device connected to CS[3] pin 27 29 Reserved Reserved 29 32 DEVWRITEINSTR Device Write Instruction Configuration Register 0x8 read-write n 0x2 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 Reserved Reserved 9 12 Reserved Reserved 18 24 Reserved Reserved 14 16 Reserved Reserved 14 16 WELDISABLE WEL Disable 8 9 WRITEDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Write Instruction 24 29 WROPCODE Write Opcode 0 8 FLASHCMDADDR Flash Command Address Register 0x94 read-write n 0x0 0xFFFFFFFF FLASHCMDCTRL Flash Command Control Register 0x90 read-write n 0x0 0xFFFFFFFF ADDRBYTENUM Number of Address Bytes 16 18 CMDADDREN Command Address Enable 19 20 CMDEXEC Execute the command 0 1 CMDEXINPROG Command execution in progress 1 2 CMDOPCODE Command Opcode 24 32 DUMCYCNUM Number of Dummy Cycles 7 12 MODEBITEN Mode Bit Enable 18 19 RDATABYTENUM Number of Read Data Bytes 20 23 RDATAEN Read Data Enable 23 24 Reserved Reserved 2 7 WRDATABYTENUM Number of Write Data Bytes 12 15 WRDATAEN Write Data Enable 15 16 FLASHCMDRDATALOW Flash Command Read Data Register (Lower) 0xA0 read-only n 0x0 0xFFFFFFFF FLASHCMDRDATAUP Flash Command Read Data Register (Upper) 0xA4 read-only n 0x0 0xFFFFFFFF FLASHCMDWRDATALOW Flash Command Write Data Register (Lower) 0xA8 read-write n 0x0 0xFFFFFFFF FLASHCMDWRDATAUP Flash Command Write Data Register (Upper) 0xAC read-write n 0x0 0xFFFFFFFF QSPICFG QSPI Configuration Register 0x0 read-write n 0x80780081 0xFFFFFFFF AHBDECEN Enable AHB Decoder 23 24 CLKPHASE Clock phase, this maps to the standard SPI CPHA transfer format 2 3 CLKPOLARITY Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format 1 2 DTREN Enable DTR Protocol 24 25 ENAHBADDRRM Enable AHB Address Re-mapping 16 17 ENDIRACCCTR Enable Direct Access Controller 7 8 ENDMAPIF Enable DMA Peripheral Interface 15 16 ENTRXIPMODEIMM Enter XIP Mode immediately 18 19 ENTRXIPMODEONR Enter XIP Mode on next READ 17 18 LEGIPMODEEN Legacy IP Mode Enable 8 9 MAMOBRDIV Master mode baud rate divisor (2 to 32) 19 23 PERCSLINES Peripheral chip select lines 10 14 ss3 n_ss_out: 0b0111 0b0111 ssinactive n_ss_out: 0b1111 (no peripheral selected) 0b1111 ss2 n_ss_out: 0b1011 0bx011 ss1 n_ss_out: 0b1101 0bxx01 ss0 n_ss_out: 0b1110 0bxxx0 PERSELDEC Peripheral select decode 9 10 Disabled Only 1 of 4 selects n_ss_out is active 0 Enabled Allow external 4-to-16 decode 1 PHYMODEEN PHY Mode enable 3 4 PIPLIDLE Serial Interface and QSPI pipeline is IDLE 31 32 PIPLPHYEN Pipeline PHY Mode enable 25 26 QSPIEN QSPI Enable 0 1 Reserved Reserved 4 7 Reserved Reserved 26 31 WPPINDRV Set to drive the WP pin of Flash device 14 15 REMAPADDR Remap Address Register 0x24 read-write n 0x0 0xFFFFFFFF QSPI_MPC QSPI Flash Memory Protection Controller SRAM_MPC 0x50120000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF S32KTIMER S32K Timer Timer 0x4002F000 0x0 0x10 registers n S32KTIMER Timer 1 2 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF S32KTIMER_Secure S32K Timer (Secure) SPI Slave 0x5002F000 0x0 0x1000 registers n FIFO_CTRL SPI Master FIFO Control Register 0x4 read-write n 0x0 0xFFFFFFFF rx_fifo_af_lvl Receive FIFO Almost Full Flag Level 8 13 read-only tx_fifo_ae_lvl Transaction FIFO Almost Empty Flag Level 0 5 read-write FIFO_STAT SPI Slave FIFO Status Information 0x8 read-write n 0x0 0xFFFFFFFF rx_fifo_used Number of Bytes in Receive FIFO 8 14 read-only tx_fifo_used Number of Bytes in Transmit FIFO 0 6 read-only GEN_CTRL SPI Slave General Control Register 0x0 read-write n 0x0 0xFFFFFFFF data_width Width of SPI Slave Data Transfers 4 6 read-write Enable read-write x1 1-bit Wide 0 x2 2-bit Wide/Dual 1 x4 4-bit Wide/Quad 2 invalid Reserved for future use. Do not use. 3 disable_parking Disable automatic resetting of SPI Slave on exit from LP Modes 31 32 read-write rx_fifo_en SPI RX FIFO Enable 2 3 read-write Enable read-write Disabled Disable SPI Slave RX FIFO 0 Enabled Enable SPI Slave RX FIFO 1 spi_mode Defines Clock Polarity (bit 17) and Clock Phase (bit 16), collectively referred to as SPI Mode. 16 18 read-write spi_slave_en SPI Slave Enable 0 1 read-write Enable read-write Disabled Disable SPI Slave 0 Enabled Enable SPI Slave 1 tx_clk_invert Invert TX Clock 20 21 read-write Enable read-write no_effect No Effect 0 Invert Inverts the TX transmit clock such that outgoing data is updated on the opposite clock edge from that specified by spi_mode. Effectively, this inverts the value of the Clock Polarity bit from the value specified in spi_mode. 1 tx_fifo_en TX FIFO Enable 1 2 read-write Enable read-write Disabled Disable SPI Slave TX FIFO 0 Enabled Enable SPI Slave TX FIFO 1 INTEN SPI Slave Interrupt Enable/Disable Settings 0x10 read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full Int Enable 1 2 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 rx_lost_data RX FIFO Overflow Int Enable 3 4 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 ss_asserted Slave Select Asserted Int Enable 5 6 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 ss_deasserted Slave Select Deasserted Int Enable 6 7 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 tx_fifo_ae TX FIFO Almost Empty Int Enable 0 1 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 tx_no_data No Data in TX FIFO Int Enable 2 3 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 tx_underflow TX Underflow Int Enable 4 5 read-write disabled Disable Interrupt 0 enabled Enable Interrupt 1 INTFL SPI Slave Interrupt Flags 0xC read-write n 0x0 0xFFFFFFFF rx_fifo_af RX FIFO Almost Full 1 2 read-write oneToClear rx_lost_data RX FIFO Overflow 3 4 read-write oneToClear ss_asserted Slave Select Asserted 5 6 read-write oneToClear ss_deasserted Slave Select Deasserted 6 7 read-write oneToClear tx_fifo_ae TX FIFO Almost Empty 0 1 read-write oneToClear tx_no_data TX FIFO Empty 2 3 read-write oneToClear S32KWATCHDOG S32K Watchdog WATCHDOG 0x4002E000 0x0 0xC04 registers n WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF S32KWATCHDOG_Secure S32K Watchdog (Secure) WATCHDOG 0x5002E000 0x0 0xC04 registers n WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF SAU Security Attribution Unit SAU 0xE000EDD0 0x0 0x20 registers n CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ALLNS Security attribution if SAU disabled 1 2 Secure Memory is marked as secure 0 Non_Secure Memory is marked as non-secure 1 ENABLE Enable 0 1 Disable SAU is disabled 0 Enable SAU is enabled 1 RBAR Region Base Address Register 0xC read-write n 0x0 0xFFFFFFFF BADDR Base Address 5 32 RLAR Region Limit Address Register 0x10 read-write n 0x0 0xFFFFFFFF ENABLE SAU Region enabled 0 1 LADDR Limit Address 5 32 NSC Non-Secure Callable 1 2 RNR Region Number Register 0x8 read-write n 0x0 0xFFFFFFFF REGION Currently selected SAU region 0 8 SAU_Region_0 Select SAU Region 0 0 SAU_Region_1 Select SAU Region 1 1 SAU_Region_2 Select SAU Region 2 2 SAU_Region_3 Select SAU Region 3 3 SFSR Secure Fault Status Register 0x14 read-write n 0x0 0xFFFFFFFF AUVIOL Attribution unit violation flag 3 4 INVEP Invalid entry pointd 0 1 INVER Invalid exception return flag 2 3 INVIS Invalid integrity signature flag 1 2 INVTRAN Invalid transition flag 4 5 LSERR Lazy state error flag 7 8 LSPERR Lazy state preservation error flag 5 6 SFARVALID Secure fault address valid 6 7 TYPE Type Register 0x4 read-only n 0x0 0xFFFFFFFF SREGION Number of implemented SAU regions 0 8 SCC Serial Communication Controller SCC 0x4010C000 0x0 0x1000 registers n CLK_CTRL 0x4 32 read-write n 0x24 0xFFFFFFFF clk_dap_en DAP clock enable 16 17 clk_llc_dap_en LLC DAP clock enable 17 18 clk_main_en Clock main enable 2 3 clk_main_sel clk_main_selw 0 2 clk_pll_in_sel 0: Pad 32K REFCLK 1: Reserved 7 8 clk_ref_en Clock ref enable 5 6 clk_ref_sel 0: REFCLK 1: FASTCLK 4 5 clk_scc_en Clock scc enable 3 4 clk_scc_sel 0: SCCCLK 1: FASTCLK 6 7 clk_test_en Test clock enable 15 16 clk_test_sel Reset Active low 12 15 PLLVCOCLK PLLVCOCLK 0 FCLK FCLK 1 SYSCLK SYSCLK 2 RM_CLK32K RM_CLK32K 3 RM_CLK32M RM_CLK32M 4 SCCCLK SCCCLK 5 Reserved Reserved 8 12 CPU0_VTOR_FLASH 0x24 32 read-write n 0x0 0xFFFFFFFF CPU0_VTOR_SRAM Reset vector for CPU0 Secure Mode 0x20 32 read-write n 0x0 0xFFFFFFFF CPU1_VTOR_FLASH 0x2C 32 read-write n 0x0 0xFFFFFFFF CPU1_VTOR_SRAM Reset vector for CPU1 Secure Mode 0x28 32 read-write n 0x0 0xFFFFFFFF CRYPTO_SRAM_RW_ASSIST0 Crypto ram pka 0xD4 32 read-write n 0x2400240 0xFFFFFFFF CRYPTO_SRAM_RW_ASSIST1 Crypto sec sram 0xD8 32 read-write n 0x2400240 0xFFFFFFFF CRYPTO_SRAM_RW_ASSIST2 Reserved 0xDC 32 read-write n 0x0 0xFFFFFFFF DBG_CTRL 0x10 32 read-write n 0x1F 0xFFFFFFFF DBGENIN DBGENIN 0 1 dbg_dcu_force 0: use Crypto DCU 1: Use SCC signal 31 32 LLCDBGENIN LLCDBGENIN 4 5 NIDENIN NIDENIN 1 2 SPIDENIN SPIDENIN 2 3 SPNIDENIN SPNIDENIN 3 4 INTR_CTRL 0x18 32 read-write n 0x0 0xFFFFFFFF ahb_ppc_irq_enable ahb_ppc_irq_enable 0 1 qspi_mpc_irq_clear qspi_mpc_irq_clear 3 4 qspi_mpc_irq_enable qspi_mpc_irq_enable 2 3 reserved reserved 1 2 sram_mpc_irq_clear sram_mpc_irq_clear 5 6 sram_mpc_irq_enable sram_mpc_irq_enable 4 5 IOMUX_ALTF1_DEFAULT_IN Default In value to Alt Function1 IPs when Alt Function1 is not selected 0x4C 32 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF1_INSEL IO Alt Function1 Input Data Select 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func1_idata_sel 1: Alt function1 of corresponding IO Selected 0 32 IOMUX_ALTF1_OENSEL IO Alt Function1 Output Enable Select 0x48 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func1_outen_sel 1: Alt function1 OEN Selected 0 32 IOMUX_ALTF1_OUTSEL IO Alt Function1 Output Data Select 0x44 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func1_odata_sel 1: Alt function1 of corresponding IO Selected 0 32 IOMUX_ALTF2_DEFAULT_IN Default In value to Alt Function2 IPs when Alt Function2 is not selected 0x5C 32 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF2_INSEL IO Alt Function2 Input Data Select 0x50 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func2_idata_sel 1: Alt function2 of corresponding IO Selected 0 32 IOMUX_ALTF2_OENSEL IO Alt Function2 Output Enable Select 0x58 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func2_outen_sel 1: Alt function2 OEN Selected 0 32 IOMUX_ALTF2_OUTSEL IO Alt Function2 Output Data Select 0x54 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func2_odata_sel 1: Alt function2 of corresponding IO Selected 0 32 IOMUX_ALTF3_DEFAULT_IN Default In value to Alt Function3 IPs when Alt Function3 is not selected 0xA0 32 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF3_INSEL IO Alt Function3 Input Data Select 0x94 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func3_idata_sel 1: Alt function3 of corresponding IO Selected 0 32 IOMUX_ALTF3_OENSEL IO Alt Function3 Output Enable Select 0x9C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func3_outen_sel 1: Alt function3 OEN Selected 0 32 IOMUX_ALTF3_OUTSEL IO Alt Function3 Output Data Select 0x98 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func3_odata_sel 1: Alt function3 of corresponding IO Selected 0 32 IOMUX_MAIN_DEFAULT_IN Default In value to main function IPs when main function is not selected 0x3C 32 read-write n 0x0 0xFFFFFFFF IOMUX_MAIN_INSEL IO Main Function Input Data Select 0x30 32 read-write n 0xFFFFFFFF 0xFFFFFFFF main_func_idata_sel 1: Main function of corresponding IO Selected 0 32 IOMUX_MAIN_OENSEL IO Main Function Output Enable Select 0x38 32 read-write n 0xFFFFFFFF 0xFFFFFFFF main_func_outen_sel 1: Main function OEN Selected 0 32 IOMUX_MAIN_OUTSEL IO Main Function Output Data Select 0x34 32 read-write n 0xFFFFFFFF 0xFFFFFFFF main_func_odata_sel 1: Main function of corresponding IO Selected 0 32 IOPAD_DS0 Drive Select0. 0x68 32 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_DS1 Drive Select1. 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_IS Input mode select 0: cmos, 1: shmitt trigger 0x7C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_PE Pull Enable 0: disabled, 1: enabled 0x70 32 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_PS Pull mode select 0: pull down, 1: pull up 0x74 32 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_SR Selw rate 0: slow, 1: fast 0x78 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PCSM_CTRL_OVEERIDE Q-Channels QACTIVE Override 0xA4 32 read-write n 0x0 0xFFFFFFFF PD_CPU0_ISO_OVEERIDE CPU0 Isolation Override 0xA8 32 read-write n 0x0 0xFFFFFFFF PD_CPU1_ISO_OVEERIDE CPU1 Isolation Override 0xAC 32 read-write n 0x0 0xFFFFFFFF PLL_CTRL 0xC 32 read-write n 0xBEB0F08 0xFFFFFFFF bypass FREF is bypassed to FOUT1 and FOUT2 1 2 fbdiv PLL Feedback divide value 16 30 foutpostdiv1pd First post divide power down. (0: ON, 1: OFF) 2 3 foutpostdiv2pd Second post divide power down. Not used 3 4 foutvcopd VCO rate output clock power down. Not used 4 5 pd Power down for PLL (0: PLL ON, 1: PLL OFF) 0 1 postdiv1 irst post divide value (for FOUT1) 8 12 postdiv2 Second post divide value (for FOUT2). Not used 12 16 PVT_CTRL PVT control register 0x60 32 read-write n 0x0 0xFFFFFFFF TSTGRPSEL TSTGRPSEL 5 6 TSTSENNUM TSTSENNUM 0 5 PWR_CTRL 0x8 32 read-write n 0x0 0xFFFFFFFF DFT_CGEN DFT_CGEN 1 2 DFT_FCLKDIVBYPASS DFT_FCLKDIVBYPASS 7 8 DFT_ISODISABLE DFT_ISODISABLE 4 5 DFT_MCPHOLD DFT_MCPHOLD 6 7 DFT_PWRUP DFT_PWRUP 5 6 DFT_RAMHOLD DFT_RAMHOLD 0 1 DFT_RSTDISABLE DFT_RSTDISABLE 2 4 DFT_SYSCLKDIVBYPASS DFT_SYSCLKDIVBYPASS 8 9 REQ_CLEAR 0x90 32 read-write n 0x0 0xFFFFFFFF clk_req_clear clk_req_clear 0 1 pwr_req_clear pwr_req_clear 1 5 REQ_EDGE_SEL Power clock request edge select 0xE0 32 read-write n 0x0 0xFFFFFFFF REQ_ENABLE Power clock request enable 0xE4 32 read-write n 0x0 0xFFFFFFFF REQ_SET 0x8C 32 read-write n 0x1 0xFFFFFFFF clk_req_set clk_req_set 0 1 pwr_req_set pwr_req_set 1 5 pwr_req_set_en pwr_req_set_en 8 12 Reserved 0xD0 32 read-write n 0x0 0xFFFFFFFF RESET_CTRL 0x0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF GPIO_RESET Reset Active low 9 10 GPTIMER_RESET Reset Active low 1 2 I2C0_RESET Reset Active low 2 3 I2C1_RESET Reset Active low 3 4 I2S_RESET Reset Active low 4 5 OTP_PSEL_ENABLE PSEL enable 17 18 OTP_RESET Reset Active low 16 17 PVT_RESET Reset Active low 10 11 PWM0_RESET Reset Active low 11 12 PWM1_RESET Reset Active low 12 13 PWM2_RESET Reset Active low 13 14 QSPI_RESET Reset Active low 6 7 RFE_RFI_RESET Reset Active low 15 16 RTC_RESET Reset Active low 14 15 SCC_RESET Reset Active low 0 1 SPI_RESET Reset Active low 5 6 UART0_RESET Reset Active low 7 8 UART1_RESET Reset Active low 8 9 SPARE0 Reserved 0x64 32 read-write n 0x0 0xFFFFFFFF SRAM_CTRL Power gate enable of SRAM blocks 0x14 32 read-write n 0x0 0xFFFFFFFF SRAM_RW_MARGINE Reserved 0x80 32 read-write n 0x0 0xFFFFFFFF STATIC_CONF_SIG0 PVT control register 0x84 32 read-write n 0x0 0xFFFFFFFF CTMCHCIHSBYPASS 0: Asynchronous, 1: Synchronous 1 5 CTMCHCISBYPASS 0: Asynchronous, 1: Synchronous 0 1 DBGENSELDIS DBGENSELDIS 5 6 LLCDBGENSELDIS LLCDBGENSELDIS 9 10 NIDENSELDIS NIDENSELDIS 6 7 SPIDENSELDIS SPIDENSELDIS 7 8 SPNIDENSELDIS SPNIDENSELDIS 8 9 STATIC_CONF_SIG1 PVT control register 0x88 32 read-write n 0x0 0xFFFFFFFF TIHSBYPASS TIHSBYPASS 12 16 TINIDENSEL TINIDENSEL 16 24 TISBYPASSACK TISBYPASSACK 8 12 TISBYPASSIN TISBYPASSIN 0 8 TODBGENSEL TODBGENSEL 24 28 SYS_SRAM_RW_ASSIST0 CPU 0 icache sram ldata assist 0xB0 32 read-write n 0x2400240 0xFFFFFFFF SYS_SRAM_RW_ASSIST1 CPU 0 icache sramtag assist 0xB4 32 read-write n 0x2400240 0xFFFFFFFF SYS_SRAM_RW_ASSIST2 CPU 1 icache ldata assist 0xB8 32 read-write n 0x2400240 0xFFFFFFFF SYS_SRAM_RW_ASSIST3 CPU 1 icache sramtag assist 0xBC 32 read-write n 0x2400240 0xFFFFFFFF SYS_SRAM_RW_ASSIST4 System sram assist 0xC0 32 read-write n 0x2400240 0xFFFFFFFF SYS_SRAM_RW_ASSIST5 System sram assist 0xC4 32 read-write n 0x4400440 0xFFFFFFFF SCC_Secure Serial Communication Controller SCC 0x5010C000 0x0 0x1000 registers n CLK_CTRL 0x4 32 read-write n 0x24 0xFFFFFFFF clk_dap_en DAP clock enable 16 17 clk_llc_dap_en LLC DAP clock enable 17 18 clk_main_en Clock main enable 2 3 clk_main_sel clk_main_selw 0 2 clk_pll_in_sel 0: Pad 32K REFCLK 1: Reserved 7 8 clk_ref_en Clock ref enable 5 6 clk_ref_sel 0: REFCLK 1: FASTCLK 4 5 clk_scc_en Clock scc enable 3 4 clk_scc_sel 0: SCCCLK 1: FASTCLK 6 7 clk_test_en Test clock enable 15 16 clk_test_sel Reset Active low 12 15 PLLVCOCLK PLLVCOCLK 0 FCLK FCLK 1 SYSCLK SYSCLK 2 RM_CLK32K RM_CLK32K 3 RM_CLK32M RM_CLK32M 4 SCCCLK SCCCLK 5 Reserved Reserved 8 12 CPU0_VTOR_FLASH 0x24 32 read-write n 0x0 0xFFFFFFFF CPU0_VTOR_SRAM Reset vector for CPU0 Secure Mode 0x20 32 read-write n 0x0 0xFFFFFFFF CPU1_VTOR_FLASH 0x2C 32 read-write n 0x0 0xFFFFFFFF CPU1_VTOR_SRAM Reset vector for CPU1 Secure Mode 0x28 32 read-write n 0x0 0xFFFFFFFF CRYPTO_SRAM_RW_ASSIST0 Crypto ram pka 0xD4 32 read-write n 0x2400240 0xFFFFFFFF CRYPTO_SRAM_RW_ASSIST1 Crypto sec sram 0xD8 32 read-write n 0x2400240 0xFFFFFFFF CRYPTO_SRAM_RW_ASSIST2 Reserved 0xDC 32 read-write n 0x0 0xFFFFFFFF DBG_CTRL 0x10 32 read-write n 0x1F 0xFFFFFFFF DBGENIN DBGENIN 0 1 dbg_dcu_force 0: use Crypto DCU 1: Use SCC signal 31 32 LLCDBGENIN LLCDBGENIN 4 5 NIDENIN NIDENIN 1 2 SPIDENIN SPIDENIN 2 3 SPNIDENIN SPNIDENIN 3 4 INTR_CTRL 0x18 32 read-write n 0x0 0xFFFFFFFF ahb_ppc_irq_enable ahb_ppc_irq_enable 0 1 qspi_mpc_irq_clear qspi_mpc_irq_clear 3 4 qspi_mpc_irq_enable qspi_mpc_irq_enable 2 3 reserved reserved 1 2 sram_mpc_irq_clear sram_mpc_irq_clear 5 6 sram_mpc_irq_enable sram_mpc_irq_enable 4 5 IOMUX_ALTF1_DEFAULT_IN Default In value to Alt Function1 IPs when Alt Function1 is not selected 0x4C 32 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF1_INSEL IO Alt Function1 Input Data Select 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func1_idata_sel 1: Alt function1 of corresponding IO Selected 0 32 IOMUX_ALTF1_OENSEL IO Alt Function1 Output Enable Select 0x48 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func1_outen_sel 1: Alt function1 OEN Selected 0 32 IOMUX_ALTF1_OUTSEL IO Alt Function1 Output Data Select 0x44 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func1_odata_sel 1: Alt function1 of corresponding IO Selected 0 32 IOMUX_ALTF2_DEFAULT_IN Default In value to Alt Function2 IPs when Alt Function2 is not selected 0x5C 32 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF2_INSEL IO Alt Function2 Input Data Select 0x50 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func2_idata_sel 1: Alt function2 of corresponding IO Selected 0 32 IOMUX_ALTF2_OENSEL IO Alt Function2 Output Enable Select 0x58 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func2_outen_sel 1: Alt function2 OEN Selected 0 32 IOMUX_ALTF2_OUTSEL IO Alt Function2 Output Data Select 0x54 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func2_odata_sel 1: Alt function2 of corresponding IO Selected 0 32 IOMUX_ALTF3_DEFAULT_IN Default In value to Alt Function3 IPs when Alt Function3 is not selected 0xA0 32 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF3_INSEL IO Alt Function3 Input Data Select 0x94 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func3_idata_sel 1: Alt function3 of corresponding IO Selected 0 32 IOMUX_ALTF3_OENSEL IO Alt Function3 Output Enable Select 0x9C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func3_outen_sel 1: Alt function3 OEN Selected 0 32 IOMUX_ALTF3_OUTSEL IO Alt Function3 Output Data Select 0x98 32 read-write n 0xFFFFFFFF 0xFFFFFFFF alt_func3_odata_sel 1: Alt function3 of corresponding IO Selected 0 32 IOMUX_MAIN_DEFAULT_IN Default In value to main function IPs when main function is not selected 0x3C 32 read-write n 0x0 0xFFFFFFFF IOMUX_MAIN_INSEL IO Main Function Input Data Select 0x30 32 read-write n 0xFFFFFFFF 0xFFFFFFFF main_func_idata_sel 1: Main function of corresponding IO Selected 0 32 IOMUX_MAIN_OENSEL IO Main Function Output Enable Select 0x38 32 read-write n 0xFFFFFFFF 0xFFFFFFFF main_func_outen_sel 1: Main function OEN Selected 0 32 IOMUX_MAIN_OUTSEL IO Main Function Output Data Select 0x34 32 read-write n 0xFFFFFFFF 0xFFFFFFFF main_func_odata_sel 1: Main function of corresponding IO Selected 0 32 IOPAD_DS0 Drive Select0. 0x68 32 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_DS1 Drive Select1. 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_IS Input mode select 0: cmos, 1: shmitt trigger 0x7C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_PE Pull Enable 0: disabled, 1: enabled 0x70 32 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_PS Pull mode select 0: pull down, 1: pull up 0x74 32 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_SR Selw rate 0: slow, 1: fast 0x78 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PCSM_CTRL_OVEERIDE Q-Channels QACTIVE Override 0xA4 32 read-write n 0x0 0xFFFFFFFF PD_CPU0_ISO_OVEERIDE CPU0 Isolation Override 0xA8 32 read-write n 0x0 0xFFFFFFFF PD_CPU1_ISO_OVEERIDE CPU1 Isolation Override 0xAC 32 read-write n 0x0 0xFFFFFFFF PLL_CTRL 0xC 32 read-write n 0xBEB0F08 0xFFFFFFFF bypass FREF is bypassed to FOUT1 and FOUT2 1 2 fbdiv PLL Feedback divide value 16 30 foutpostdiv1pd First post divide power down. (0: ON, 1: OFF) 2 3 foutpostdiv2pd Second post divide power down. Not used 3 4 foutvcopd VCO rate output clock power down. Not used 4 5 pd Power down for PLL (0: PLL ON, 1: PLL OFF) 0 1 postdiv1 irst post divide value (for FOUT1) 8 12 postdiv2 Second post divide value (for FOUT2). Not used 12 16 PVT_CTRL PVT control register 0x60 32 read-write n 0x0 0xFFFFFFFF TSTGRPSEL TSTGRPSEL 5 6 TSTSENNUM TSTSENNUM 0 5 PWR_CTRL 0x8 32 read-write n 0x0 0xFFFFFFFF DFT_CGEN DFT_CGEN 1 2 DFT_FCLKDIVBYPASS DFT_FCLKDIVBYPASS 7 8 DFT_ISODISABLE DFT_ISODISABLE 4 5 DFT_MCPHOLD DFT_MCPHOLD 6 7 DFT_PWRUP DFT_PWRUP 5 6 DFT_RAMHOLD DFT_RAMHOLD 0 1 DFT_RSTDISABLE DFT_RSTDISABLE 2 4 DFT_SYSCLKDIVBYPASS DFT_SYSCLKDIVBYPASS 8 9 REQ_CLEAR 0x90 32 read-write n 0x0 0xFFFFFFFF clk_req_clear clk_req_clear 0 1 pwr_req_clear pwr_req_clear 1 5 REQ_EDGE_SEL Power clock request edge select 0xE0 32 read-write n 0x0 0xFFFFFFFF REQ_ENABLE Power clock request enable 0xE4 32 read-write n 0x0 0xFFFFFFFF REQ_SET 0x8C 32 read-write n 0x1 0xFFFFFFFF clk_req_set clk_req_set 0 1 pwr_req_set pwr_req_set 1 5 pwr_req_set_en pwr_req_set_en 8 12 Reserved 0xD0 32 read-write n 0x0 0xFFFFFFFF RESET_CTRL 0x0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF GPIO_RESET Reset Active low 9 10 GPTIMER_RESET Reset Active low 1 2 I2C0_RESET Reset Active low 2 3 I2C1_RESET Reset Active low 3 4 I2S_RESET Reset Active low 4 5 OTP_PSEL_ENABLE PSEL enable 17 18 OTP_RESET Reset Active low 16 17 PVT_RESET Reset Active low 10 11 PWM0_RESET Reset Active low 11 12 PWM1_RESET Reset Active low 12 13 PWM2_RESET Reset Active low 13 14 QSPI_RESET Reset Active low 6 7 RFE_RFI_RESET Reset Active low 15 16 RTC_RESET Reset Active low 14 15 SCC_RESET Reset Active low 0 1 SPI_RESET Reset Active low 5 6 UART0_RESET Reset Active low 7 8 UART1_RESET Reset Active low 8 9 SPARE0 Reserved 0x64 32 read-write n 0x0 0xFFFFFFFF SRAM_CTRL Power gate enable of SRAM blocks 0x14 32 read-write n 0x0 0xFFFFFFFF SRAM_RW_MARGINE Reserved 0x80 32 read-write n 0x0 0xFFFFFFFF STATIC_CONF_SIG0 PVT control register 0x84 32 read-write n 0x0 0xFFFFFFFF CTMCHCIHSBYPASS 0: Asynchronous, 1: Synchronous 1 5 CTMCHCISBYPASS 0: Asynchronous, 1: Synchronous 0 1 DBGENSELDIS DBGENSELDIS 5 6 LLCDBGENSELDIS LLCDBGENSELDIS 9 10 NIDENSELDIS NIDENSELDIS 6 7 SPIDENSELDIS SPIDENSELDIS 7 8 SPNIDENSELDIS SPNIDENSELDIS 8 9 STATIC_CONF_SIG1 PVT control register 0x88 32 read-write n 0x0 0xFFFFFFFF TIHSBYPASS TIHSBYPASS 12 16 TINIDENSEL TINIDENSEL 16 24 TISBYPASSACK TISBYPASSACK 8 12 TISBYPASSIN TISBYPASSIN 0 8 TODBGENSEL TODBGENSEL 24 28 SYS_SRAM_RW_ASSIST0 CPU 0 icache sram ldata assist 0xB0 32 read-write n 0x2400240 0xFFFFFFFF SYS_SRAM_RW_ASSIST1 CPU 0 icache sramtag assist 0xB4 32 read-write n 0x2400240 0xFFFFFFFF SYS_SRAM_RW_ASSIST2 CPU 1 icache ldata assist 0xB8 32 read-write n 0x2400240 0xFFFFFFFF SYS_SRAM_RW_ASSIST3 CPU 1 icache sramtag assist 0xBC 32 read-write n 0x2400240 0xFFFFFFFF SYS_SRAM_RW_ASSIST4 System sram assist 0xC0 32 read-write n 0x2400240 0xFFFFFFFF SYS_SRAM_RW_ASSIST5 System sram assist 0xC4 32 read-write n 0x4400440 0xFFFFFFFF SPCTRL Secure Privilege Control Block SPCTRL 0x50080000 0x0 0x1000 registers n AHBNSPPC0 Non-Secure Access AHB slave Peripheral Protection Control 0 0x50 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP0 Expansion 0 Non_Secure Access AHB slave Peripheral Protection Control 0x60 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP1 Expansion 1 Non_Secure Access AHB slave Peripheral Protection Control 0x64 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP2 Expansion 2 Non_Secure Access AHB slave Peripheral Protection Control 0x68 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP3 Expansion 3 Non_Secure Access AHB slave Peripheral Protection Control 0x6C 32 read-write n 0x0 0xFFFFFFFF AHBSPPPC0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0 0x90 32 read-only n 0x0 0xFFFFFFFF AHBSPPPCEXP0 Expansion 0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 32 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP1 Expansion 1 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 32 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP2 Expansion 2 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 32 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP3 Expansion 3 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC 32 read-write n 0x0 0xFFFFFFFF APBNSPPC0 Non-Secure Access APB slave Peripheral Protection Control 0 0x70 32 read-write n 0x0 0xFFFFFFFF APBNSPPC1 Non-Secure Access APB slave Peripheral Protection Control 1 0x74 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP0 Expansion 0 Non_Secure Access APB slave Peripheral Protection Control 0x80 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP1 Expansion 1 Non_Secure Access APB slave Peripheral Protection Control 0x84 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP2 Expansion 2 Non_Secure Access APB slave Peripheral Protection Control 0x88 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP3 Expansion 3 Non_Secure Access APB slave Peripheral Protection Control 0x8C 32 read-write n 0x0 0xFFFFFFFF APBSPPPC0 Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 32 read-write n 0x0 0xFFFFFFFF APBSPPPC1 Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP0 Expansion 0 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP1 Expansion 1 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP2 Expansion 2 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP3 Expansion 3 Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC 32 read-write n 0x0 0xFFFFFFFF BRGINTCLR Bridge Buffer Error Interrupt Clear 0x44 32 write-only n 0x0 0xFFFFFFFF BRGINTEN Bridge Buffer Error Interrupt Enable 0x48 32 read-write n 0x0 0xFFFFFFFF BRGINTSTAT Bridge Buffer Error Interrupt Status 0x40 32 read-only n 0x0 0xFFFFFFFF BUSWAIT Bus Access wait control after reset 0x4 32 read-write n 0x0 0xFFFFFFFF CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF NSCCFG Non Secure Callable Configuration for IDAU 0x14 32 read-write n 0x0 0xFFFFFFFF NSMSCEXP Expansion MSC Non-Secure Configuration 0xD0 32 read-only n 0x0 0xFFFFFFFF PID0 Peripheral ID 0 0xFE0 32 read-only n 0x52 0xFFFFFFFF PID1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PID2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF PID3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF PID4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF SECMPCINTSTATUS Secure MPC Interrupt Status 0x1C 32 read-only n 0x0 0xFFFFFFFF SECMSCINTCLR Secure MSC Interrupt Clear 0x34 32 read-write n 0x0 0xFFFFFFFF SECMSCINTEN Secure MSC Interrupt Enable 0x38 32 read-write n 0x0 0xFFFFFFFF SECMSCINTSTAT Secure MSC Interrupt Status 0x30 32 read-only n 0x0 0xFFFFFFFF SECPPCINTCLR Secure PPC Interrupt Clear 0x24 32 write-only n 0x0 0xFFFFFFFF SECPPCINTEN Secure PPC Interrupt Enable 0x28 32 read-write n 0x0 0xFFFFFFFF SECPPCINTSTAT Secure PPC Interrupt Status 0x20 32 read-only n 0x0 0xFFFFFFFF SECRESPCFG Security Violation Response Configuration register 0x10 32 read-write n 0x0 0xFFFFFFFF SPCSECTRL Secure Privilege Controller Secure Configuration Control register 0x0 32 read-write n 0x0 0xFFFFFFFF SPI0 SPI 0 SPI 0x40103000 0x0 0xFC registers n SPIINTR0 SPI0 interrupt 37 SPICR Control register 0x0 read-write n 0x20000 0xFFFFFFFF CPHA Clock Phase: Selects whether the SPI clock is in active or inactive phase outside the SPI word 2 1 CPOL External Clock Edge: Selects the SPI clock polarity outside SPI word 1 1 MBRD Master Baud Rate Divisor (2 to 256). The SCLK is generated base on SPI REFERENCE CLOCK or ext_clk divided by MBRD 3 3 MCSE Manual Chip Select Enable: When this bit is set, the n_ss_out[3:0] lines will be driven permanently by the encoded peripheral select value regardless of the current state of the main SPI state machine 14 1 MFGE Mode Fail Generation Enable: When this bit is set the logic generating Mode Fail is enabled 17 1 MRCS Reference Clock Select: When this bit is set the ext_clk is used, otherwise SPI REFERENCE CLOCK is used 8 1 MSC Manual Start Command: When manual start mode is enabled (see Manual Start Enable bit of Configuration Register) and TX FIFO is not empty, writing a ‘1’ to this bit will start transmission. Writing a '0' will have no effect. It returns ‘0’ when read 16 1 MSE Manual Start Enable: When this bit is set do not allow transmission to start until Manual Start Command (see MSC) bit is written with a '1' 15 1 MSEL Mode Select: Selects SPI controller mode (MASTER/SLAVE) 0 1 PCSL Peripheral Chip Select Lines (master mode only): When Peripheral Select Decode is set then PCSL[3:0] directly drives n_ss_out [3:0], else (PSD is written with ‘0’) PCSL[3:0] drives n_ss_out [3:0] 10 4 PSD Peripheral Select Decode: When this bit is set allow external 4-to-16 decode (n_ss_out [3:0 = PCSL [3:0]). When Peripheral Select Decode is not set, only 1 of 4 selects n_ss_out[3:0] are active (see PCSL) 9 1 RXCLR RX FIFO Clear: Writing a ‘1’ to this bit will clear the RX FIFO. Writing a '0' will have no effect. It returns ‘0’ when read 19 1 SPSE Sample Point Shift Enable: When this bit is set and controller is in MASTER receiver mode then sample point of receiving data is shifted with respect to sample point of SPI protocol specification 18 1 TWS Transfer Word Size: Define size of word to be transferred. This MUST be equal to the FIFO width (FF_W), or a sub-multiple of FF_W to allow multiple word transfers per FIFO word 6 2 TXCLR TX FIFO Clear: Writing a ‘1’ to this bit will clear the TX FIFO. Writing a '0' will have no effect. It returns ‘0’ when read 20 1 SPIENR SPI Enable Register 0x14 read-write n 0x0 0xFFFFFFFF SPIE SPI Enable: When this bit is set the SPI controller is enabled, otherwise SPI is disabled. When SPI controller is disabled all output enables are inactive and all pins are set to input mode. Writing ‘0’ disables the SPI controller once current transfer of the data word (FF_W) is complete 0 1 SPIIDR Interrupt Disable Register 0xC -1 write-only n 0x0 0xFFFFFFFF MFD Mode Fail Disable 1 1 RFD RX FIFO Full Disable 5 1 RNED RX FIFO Not Empty Disable 4 1 ROFD RX FIFO Overflow Disable 0 1 TFD TX FIFO Full Disable 3 1 TNFD TX FIFO Not Full Disable 2 1 TUFD TX FIFO Underflow Disable 6 1 SPIIER Interrupt Enable Register 0x8 -1 write-only n 0x0 0xFFFFFFFF MFE Mode Fail Enable 1 1 RFE RX FIFO Full Enable 5 1 RNEE RX FIFO Not Empty Enable 4 1 ROFE RX FIFO Overflow Enable 0 1 TFE TX FIFO Full Enable 3 1 TNFE TX FIFO Not Full Enable 2 1 TUFE TX FIFO Underflow Enable 6 1 SPIIMR Interrupt Mask Register 0x10 -1 read-only n 0x0 0xFFFFFFFF MFM Mode Fail Mask 1 1 RFM RX FIFO Full Mask 5 1 RNEM RX FIFO Not Empty Mask 4 1 ROFM RX FIFO Overflow Mask 0 1 TFM TX FIFO Full Mask 3 1 TNFM TX FIFO Not Full Mask 2 1 TUFM TX FIFO Underflow Mask 6 1 SPIISR Interrupt Status Register 0x4 -1 read-only n 0x4 0xFFFFFFFF MF Mode Fail: Indicates the voltage on pin n_ss_in is inconsistent with the SPI mode 1 1 RF RX FIFO Full (current FIFO status) 5 1 RNE RX FIFO Not Empty (current FIFO status) 4 1 ROF RX FIFO Overflow: This bit is set if an attempt is made to push the RX FIFO when it is full 0 1 TF TX FIFO Full (current FIFO status) 3 1 TNF TX FIFO Not Full (current FIFO status) 2 1 TUF TX FIFO Underflow: This bit is reset only by a system reset and cleared only when the register is read 6 1 SPIRDR Receive Data Register 0x20 -1 read-only n 0x0 0xFFFFFFFF RDATA Receive Data: Reads the RX FIFO location indicated by the current read address and then increments the read address 0 8 SPITDR Transmit Data Register 0x1C -1 write-only n 0x0 0xFFFFFFFF TDATA Transmit Data: Writes to the TX FIFO location indicated by its internal write address and increments the write address by pushing it 0 8 SRAM0MPC Memory Protection Controller 0 SRAM_MPC 0x50083000 0x0 0x1000 registers n MPC MPC Combined 9 BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SRAM1MPC SRAM 1 Memory Protection Controller SRAM_MPC 0x50084000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SRAM2MPC SRAM 2 Memory Protection Controller SRAM_MPC 0x50085000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SRAM3MPC SRAM 3 Memory Protection Controller SRAM_MPC 0x50086000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF TIMER0 Timer 0 Timer 0x40000000 0x0 0x10 registers n TIMER0 Timer 0 3 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER0_Secure Timer 0 (Secure) Timer 0x50000000 0x0 0x10 registers n CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER1 Timer 1 Timer 0x40001000 0x0 0x10 registers n TIMER1 Timer 1 4 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER1_Secure Timer 1 (Secure) ADC 0x50001000 0x0 0x1000 registers n AFE_CTRL AFE Control Register 0x20 read-write n 0x0 0xFFFFFFFF tmon_extbias_en Enable external temperature measurement bias generator 9 10 read-write tmon_intbias_en Enable internal temperature measurement bias generator 8 9 read-write CTRL ADC Control 0x0 read-write n 0x0 0xFFFFFFFF adc_chgpump_pu ADC Charge Pump Power Up 4 5 read-write adc_chsel ADC Channel Select 12 16 read-write adc_clk_en ADC Clock Enable 11 12 read-write adc_dataalign ADC Data Alignment Select 17 18 read-write adc_pu ADC Power Up 1 2 read-write adc_refbuf_pu ADC Reference Buffer Power Up 3 4 read-write adc_refscl ADC Reference Scale 8 9 read-write adc_refsel ADC Reference (VRef) Select (INTERNAL ONLY) 10 11 read-write adc_scale ADC Scale 9 10 read-write adc_xref Enable Use of ADC External Reference 16 17 read-write afe_pwr_up_dly Delay from ADC Powerup Until ADC Ready Asserted 24 32 read-write buf_bypass Bypass Input Buffer 7 8 read-write buf_chop_dis ADC Input Buffer Chop Disable (INTERNAL ONLY) 5 6 read-write buf_pu ADC Input Buffer Power Up 2 3 read-write buf_pump_dis Disable Use of Charge Pump Output by Input Buffer (INTERNAL) 6 7 read-write cpu_adc_start Start ADC Conversion 0 1 read-write DATA ADC Output Data 0x8 read-write n 0x0 0xFFFFFFFF adc_data ADC Converted Sample Data Output 0 16 read-only INTR ADC Interrupt Control Register 0xC read-write n 0x0 0xFFFFFFFF adc_done_ie ADC Done Interrupt Enable 0 1 read-write adc_done_if ADC Done Interrupt Flag 16 17 read-write oneToClear adc_hi_limit_ie ADC Hi Limit Monitor Interrupt Enable 2 3 read-write adc_hi_limit_if ADC Hi Limit Monitor Interrupt Flag 18 19 read-write oneToClear adc_int_pending ADC Interrupt Pending Status 22 23 read-only adc_lo_limit_ie ADC Lo Limit Monitor Interrupt Enable 3 4 read-write adc_lo_limit_if ADC Lo Limit Monitor Interrupt Flag 19 20 read-write oneToClear adc_overflow_ie ADC Overflow Interrupt Enable 4 5 read-write adc_overflow_if ADC Overflow Interrupt Flag 20 21 read-write oneToClear adc_ref_ready_ie ADC Reference Ready Interrupt Enable 1 2 read-write adc_ref_ready_if ADC Reference Ready Interrupt Flag 17 18 read-write oneToClear ro_cal_done_ie RO Cal Done Interrupt Enable 5 6 read-write ro_cal_done_if RO Cal Done Interrupt Flag 21 22 read-write oneToClear LIMIT0 ADC Limit 0x10 read-write n 0x0 0xFFFFFFFF ch_hi_limit High Limit Threshold 12 22 read-write ch_hi_limit_en High Limit Monitoring Enable 29 30 read-write ch_lo_limit Low Limit Threshold 0 10 read-write ch_lo_limit_en Low Limit Monitoring Enable 28 29 read-write ch_sel ADC Channel Select 24 28 read-write LIMIT1 ADC Limit 1 0x14 read-write n 0x0 0xFFFFFFFF ch_hi_limit High Limit Threshold 12 22 read-write ch_hi_limit_en High Limit Monitoring Enable 29 30 read-write ch_lo_limit Low Limit Threshold 0 10 read-write ch_lo_limit_en Low Limit Monitoring Enable 28 29 read-write ch_sel ADC Channel Select 24 28 read-write LIMIT2 ADC Limit 2 0x18 read-write n 0x0 0xFFFFFFFF ch_hi_limit High Limit Threshold 12 22 read-write ch_hi_limit_en High Limit Monitoring Enable 29 30 read-write ch_lo_limit Low Limit Threshold 0 10 read-write ch_lo_limit_en Low Limit Monitoring Enable 28 29 read-write ch_sel ADC Channel Select 24 28 read-write LIMIT3 ADC Limit 3 0x1C read-write n 0x0 0xFFFFFFFF ch_hi_limit High Limit Threshold 12 22 read-write ch_hi_limit_en High Limit Monitoring Enable 29 30 read-write ch_lo_limit Low Limit Threshold 0 10 read-write ch_lo_limit_en Low Limit Monitoring Enable 28 29 read-write ch_sel ADC Channel Select 24 28 read-write RO_CAL0 RO Trim Calibration Register 0 0x24 read-write n 0x0 0xFFFFFFFF dummy Dummy Write Field 5 8 read-write ro_cal_atomic RO Calibration Run Atomic 4 5 read-write ro_cal_en RO Calibration Enable 0 1 read-write ro_cal_load RO Calibration Load Initial Value 2 3 read-write ro_cal_run RO Calibration Run 1 2 read-write ro_trm RO Trim Calibration Result 23 32 read-write trm_mu RO Trim Adaptation Gain 8 20 read-write RO_CAL1 RO Trim Calibration Register 1 0x28 read-write n 0x0 0xFFFFFFFF trm_init RO Trim Initial Value 0 9 read-write trm_max RO Trim Minimum Adaptive Limit 20 29 read-write trm_min RO Trim Maximum Adaptive Limit 10 19 read-write RO_CAL2 RO Trim Calibration Register 2 0x2C read-write n 0x0 0xFFFFFFFF auto_cal_done_cnt Auto Cal Time Delay for Atomic Calibration (in milliseconds) 0 8 read-write STATUS ADC Status 0x4 read-write n 0x0 0xFFFFFFFF adc_active ADC Conversion In Progress 0 1 read-only adc_overflow ADC Overflow 3 4 read-only afe_pwr_up_active AFE Power Up Delay Active 2 3 read-only ro_cal_atomic_active RO Frequency Calibration Active (If Atomic) 1 2 read-only UART0 UART 0 UART 0x40101000 0x0 0x4C registers n UARTINTR0 UART0 interrupt 44 UARTCR Control register 0x30 read-write n 0x300 0xFFFFFFFF CTSEn CTS hardware flow control enable 15 1 Disable CTS hardware flow control is disabled 0 Enable CTS hardware flow control is enabled 1 DTR Data transmit ready 10 1 LBE Loop back enable 7 1 Disable Loop back mode is disabled 0 Enable Loop back mode is enabled 1 Out1 Complement of the UART Out1 12 1 Out2 Complement of the UART Out2 13 1 RTS Request to send 11 1 RTSEn RTS hardware flow control enable 14 1 Disable RTS hardware flow control is disabled 0 Enable RTS hardware flow control is enabled 1 RXE Receive enable 9 1 Disable Reception is disabled 0 Enable Reception is enabled 1 SIREN SIR enable 1 1 Disable SIR is disabled 0 Enable SIR is enabled 1 SIRLP IrDA SIR low power mode 2 1 Disable SIR low power mode is disabled 0 Enable SIR low power mode is enabled 1 TXE Transmit enable 8 1 Disable Transmission is disabled. 0 Enable Transmission is enabled. 1 UARTEN UART enable 0 1 Disable UART is disabled 0 Enable UART is enabled 1 UARTDMACR DMA control register 0x48 read-write n 0x0 0xFFFFFFFF DMAONERR DMA on error 2 1 Disable DMA receive request outputs are enabled when the UART error interrupt is asserted 0 Enable DMA receive request outputs are disabled when the UART error interrupt is asserted 1 RXDMAE Receive DMA enable 0 1 Disable Receive DMA is disabled 0 Enable Receive DMA is enabled 1 TXDMAE Transmit DMA enable 1 1 Disable Transmit DMA is disabled 0 Enable Transmit DMA is enabled 1 UARTDR Data register 0x0 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 10 1 Data Receive/Transmit data 0 8 FE Framing error: Indicates the received character did not had a valid stop bit 8 1 OE Overrun error: Indicates if data is received and the receive FIFO is already full. 11 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 9 1 UARTFBRD Fractional baud rate register 0x28 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 6 UARTIBRD Integer baud rate register 0x24 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 16 UARTICR Interrupt clear register 0x44 write-only n 0x0 0xFFFFFFFF BEIC Break error interrupt clear, write 1 to clear, write 0 has no effect 9 1 CTSMIC nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect 1 1 DCDMIC nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect 2 1 DSRIC nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect 3 1 FEIC Framing error interrupt clear, write 1 to clear, write 0 has no effect 7 1 OEIC Overrun error interrupt clear, write 1 to clear, write 0 has no effect 10 1 PEIC Parity error interrupt clear, write 1 to clear, write 0 has no effect 8 1 RIMIC nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect 0 1 RTIC Receive timeout interrupt clear, write 1 to clear, write 0 has no effect 6 1 RXIC Receive interrupt clear, write 1 to clear, write 0 has no effect 4 1 TXIC Transmit interrupt clear, write 1 to clear, write 0 has no effect 5 1 UARTIFLS Interrupt FIFO level select register 0x34 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive interrupt FIFO level select 3 3 1/8 full Receive FIFO becomes greater than or equal to 1/8 full 0 1/4 full Receive FIFO becomes greater than or equal to 1/4 full 1 1/2 full Receive FIFO becomes greater than or equal to 1/2 full 2 3/4 full Receive FIFO becomes greater than or equal to 3/4 full 3 7/8 full Receive FIFO becomes greater than or equal to 7/8 full 4 TXIFLSEL Transmit interrupt FIFO level select 0 3 1/8 full Transmit FIFO becomes less than or equal to 1/8 full 0 1/4 full Transmit FIFO becomes less than or equal to 1/4 full 1 1/2 full Transmit FIFO becomes less than or equal to 1/2 full 2 3/4 full Transmit FIFO becomes less than or equal to 3/4 full 3 7/8 full Transmit FIFO becomes less than or equal to 7/8 full 4 UARTILPR IrDA low-power counter register 0x20 read-write n 0x0 0xFFFFFFFF ILPDVSR 8-bit low-power divisor value 0 8 UARTIMSC Interrupt mask set/clear register 0x38 read-write n 0x0 0xFFFFFFFF BEIM Break error interrupt mask 9 1 Clear Clears the mask 0 Set Sets the mask 1 CTSMIM nUARTCTS modem interrupt mask. 1 1 Clear Clears the mask 0 Set Sets the mask 1 DCDMIM nUARTDCD modem interrupt mask 2 1 Clear Clears the mask 0 Set Sets the mask 1 DSRMIM nUARTDSR modem interrupt mask 3 1 Clear Clears the mask 0 Set Sets the mask 1 FEIM Framing error interrupt mask 7 1 Clear Clears the mask 0 Set Sets the mask 1 OEIM Overrun error interrupt mask 10 1 Clear Clears the mask 0 Set Sets the mask 1 PEIM Parity error interrupt mask 8 1 Clear Clears the mask 0 Set Sets the mask 1 RIMIM nUARTRI modem interrupt mask 0 1 Clear Clears the mask 0 Set Sets the mask 1 RTIM Receive timeout interrupt mask 6 1 Clear Clears the mask 0 Set Sets the mask 1 RXIM Receive interrupt mask 4 1 Clear Clears the mask 0 Set Sets the mask 1 TXIM Transmit interrupt mask 5 1 Clear Clears the mask 0 Set Sets the mask 1 UARTLCR_H Line control register 0x2C read-write n 0x0 0xFFFFFFFF BRK Send break 0 1 EPS Even parity select 2 1 FEN Enable FIFOs 4 1 PEN Parity enable 1 1 SPS Stick parity select 7 1 STP2 Two stop bits select 3 1 WLEN Word length 5 2 UARTMIS Masked interrupt status register 0x40 read-only n 0x0 0xFFFFFFFF BEMIS Break error masked interrupt status 9 1 CTSMMIS nUARTCTS modem masked interrupt status. 1 1 DCDMMIS nUARTDCD modem masked interrupt status 2 1 DSRMMIS nUARTDSR modem masked interrupt status 3 1 FEMIS Framing error masked interrupt status 7 1 OEMIS Overrun error masked interrupt status 10 1 PEMIS Parity error masked interrupt status 8 1 RIMMIS nUARTRI modem masked interrupt status 0 1 RTMIS Receive timeout masked interrupt status 6 1 RXMIS Receive masked interrupt status 4 1 TXMIS Transmit masked interrupt status 5 1 UARTRFR Flag register 0x18 read-only n 0x0 0xFFFFFFFF BUSY UART busy 3 1 CTS Clear to send 0 1 DCD Data carrier detect 2 1 DSR Data set ready 1 1 RI Ring indicator 8 1 RXFE Receive FIFO empty 4 1 RXFF Receive FIFO full 6 1 TXFE Transmit FIFO empty 7 1 TXFF Transmit FIFO full 5 1 UARTRIS Raw interrupt status register 0x3C read-only n 0x0 0xFFFFFFFF BERIS Break error interrupt status 9 1 CTSRMIS nUARTCTS modem interrupt status. 1 1 DCDRMIS nUARTDCD modem interrupt status 2 1 DSRRMIS nUARTDSR modem interrupt status 3 1 FERIS Framing error interrupt status 7 1 OERIS Overrun error interrupt status 10 1 PERIS Parity error interrupt status 8 1 RIRMIS nUARTRI modem interrupt status 0 1 RTRIS Receive timeout interrupt status 6 1 RXRIS Receive interrupt status 4 1 TXRIS Transmit interrupt status 5 1 UARTRSR_UARTECR Receive status register/error clear register 0x4 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 2 1 FE Framing error: Indicates the received character did not had a valid stop bit 0 1 OE Overrunerror: Indicates if data is received and the receive FIFO is already full. 3 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 1 1 UART0_Secure UART 0 (Secure) UART 0x50101000 0x0 0x4C registers n UARTCR Control register 0x30 read-write n 0x300 0xFFFFFFFF CTSEn CTS hardware flow control enable 15 1 Disable CTS hardware flow control is disabled 0 Enable CTS hardware flow control is enabled 1 DTR Data transmit ready 10 1 LBE Loop back enable 7 1 Disable Loop back mode is disabled 0 Enable Loop back mode is enabled 1 Out1 Complement of the UART Out1 12 1 Out2 Complement of the UART Out2 13 1 RTS Request to send 11 1 RTSEn RTS hardware flow control enable 14 1 Disable RTS hardware flow control is disabled 0 Enable RTS hardware flow control is enabled 1 RXE Receive enable 9 1 Disable Reception is disabled 0 Enable Reception is enabled 1 SIREN SIR enable 1 1 Disable SIR is disabled 0 Enable SIR is enabled 1 SIRLP IrDA SIR low power mode 2 1 Disable SIR low power mode is disabled 0 Enable SIR low power mode is enabled 1 TXE Transmit enable 8 1 Disable Transmission is disabled. 0 Enable Transmission is enabled. 1 UARTEN UART enable 0 1 Disable UART is disabled 0 Enable UART is enabled 1 UARTDMACR DMA control register 0x48 read-write n 0x0 0xFFFFFFFF DMAONERR DMA on error 2 1 Disable DMA receive request outputs are enabled when the UART error interrupt is asserted 0 Enable DMA receive request outputs are disabled when the UART error interrupt is asserted 1 RXDMAE Receive DMA enable 0 1 Disable Receive DMA is disabled 0 Enable Receive DMA is enabled 1 TXDMAE Transmit DMA enable 1 1 Disable Transmit DMA is disabled 0 Enable Transmit DMA is enabled 1 UARTDR Data register 0x0 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 10 1 Data Receive/Transmit data 0 8 FE Framing error: Indicates the received character did not had a valid stop bit 8 1 OE Overrun error: Indicates if data is received and the receive FIFO is already full. 11 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 9 1 UARTFBRD Fractional baud rate register 0x28 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 6 UARTIBRD Integer baud rate register 0x24 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 16 UARTICR Interrupt clear register 0x44 write-only n 0x0 0xFFFFFFFF BEIC Break error interrupt clear, write 1 to clear, write 0 has no effect 9 1 CTSMIC nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect 1 1 DCDMIC nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect 2 1 DSRIC nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect 3 1 FEIC Framing error interrupt clear, write 1 to clear, write 0 has no effect 7 1 OEIC Overrun error interrupt clear, write 1 to clear, write 0 has no effect 10 1 PEIC Parity error interrupt clear, write 1 to clear, write 0 has no effect 8 1 RIMIC nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect 0 1 RTIC Receive timeout interrupt clear, write 1 to clear, write 0 has no effect 6 1 RXIC Receive interrupt clear, write 1 to clear, write 0 has no effect 4 1 TXIC Transmit interrupt clear, write 1 to clear, write 0 has no effect 5 1 UARTIFLS Interrupt FIFO level select register 0x34 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive interrupt FIFO level select 3 3 1/8 full Receive FIFO becomes greater than or equal to 1/8 full 0 1/4 full Receive FIFO becomes greater than or equal to 1/4 full 1 1/2 full Receive FIFO becomes greater than or equal to 1/2 full 2 3/4 full Receive FIFO becomes greater than or equal to 3/4 full 3 7/8 full Receive FIFO becomes greater than or equal to 7/8 full 4 TXIFLSEL Transmit interrupt FIFO level select 0 3 1/8 full Transmit FIFO becomes less than or equal to 1/8 full 0 1/4 full Transmit FIFO becomes less than or equal to 1/4 full 1 1/2 full Transmit FIFO becomes less than or equal to 1/2 full 2 3/4 full Transmit FIFO becomes less than or equal to 3/4 full 3 7/8 full Transmit FIFO becomes less than or equal to 7/8 full 4 UARTILPR IrDA low-power counter register 0x20 read-write n 0x0 0xFFFFFFFF ILPDVSR 8-bit low-power divisor value 0 8 UARTIMSC Interrupt mask set/clear register 0x38 read-write n 0x0 0xFFFFFFFF BEIM Break error interrupt mask 9 1 Clear Clears the mask 0 Set Sets the mask 1 CTSMIM nUARTCTS modem interrupt mask. 1 1 Clear Clears the mask 0 Set Sets the mask 1 DCDMIM nUARTDCD modem interrupt mask 2 1 Clear Clears the mask 0 Set Sets the mask 1 DSRMIM nUARTDSR modem interrupt mask 3 1 Clear Clears the mask 0 Set Sets the mask 1 FEIM Framing error interrupt mask 7 1 Clear Clears the mask 0 Set Sets the mask 1 OEIM Overrun error interrupt mask 10 1 Clear Clears the mask 0 Set Sets the mask 1 PEIM Parity error interrupt mask 8 1 Clear Clears the mask 0 Set Sets the mask 1 RIMIM nUARTRI modem interrupt mask 0 1 Clear Clears the mask 0 Set Sets the mask 1 RTIM Receive timeout interrupt mask 6 1 Clear Clears the mask 0 Set Sets the mask 1 RXIM Receive interrupt mask 4 1 Clear Clears the mask 0 Set Sets the mask 1 TXIM Transmit interrupt mask 5 1 Clear Clears the mask 0 Set Sets the mask 1 UARTLCR_H Line control register 0x2C read-write n 0x0 0xFFFFFFFF BRK Send break 0 1 EPS Even parity select 2 1 FEN Enable FIFOs 4 1 PEN Parity enable 1 1 SPS Stick parity select 7 1 STP2 Two stop bits select 3 1 WLEN Word length 5 2 UARTMIS Masked interrupt status register 0x40 read-only n 0x0 0xFFFFFFFF BEMIS Break error masked interrupt status 9 1 CTSMMIS nUARTCTS modem masked interrupt status. 1 1 DCDMMIS nUARTDCD modem masked interrupt status 2 1 DSRMMIS nUARTDSR modem masked interrupt status 3 1 FEMIS Framing error masked interrupt status 7 1 OEMIS Overrun error masked interrupt status 10 1 PEMIS Parity error masked interrupt status 8 1 RIMMIS nUARTRI modem masked interrupt status 0 1 RTMIS Receive timeout masked interrupt status 6 1 RXMIS Receive masked interrupt status 4 1 TXMIS Transmit masked interrupt status 5 1 UARTRFR Flag register 0x18 read-only n 0x0 0xFFFFFFFF BUSY UART busy 3 1 CTS Clear to send 0 1 DCD Data carrier detect 2 1 DSR Data set ready 1 1 RI Ring indicator 8 1 RXFE Receive FIFO empty 4 1 RXFF Receive FIFO full 6 1 TXFE Transmit FIFO empty 7 1 TXFF Transmit FIFO full 5 1 UARTRIS Raw interrupt status register 0x3C read-only n 0x0 0xFFFFFFFF BERIS Break error interrupt status 9 1 CTSRMIS nUARTCTS modem interrupt status. 1 1 DCDRMIS nUARTDCD modem interrupt status 2 1 DSRRMIS nUARTDSR modem interrupt status 3 1 FERIS Framing error interrupt status 7 1 OERIS Overrun error interrupt status 10 1 PERIS Parity error interrupt status 8 1 RIRMIS nUARTRI modem interrupt status 0 1 RTRIS Receive timeout interrupt status 6 1 RXRIS Receive interrupt status 4 1 TXRIS Transmit interrupt status 5 1 UARTRSR_UARTECR Receive status register/error clear register 0x4 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 2 1 FE Framing error: Indicates the received character did not had a valid stop bit 0 1 OE Overrunerror: Indicates if data is received and the receive FIFO is already full. 3 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 1 1 UART1 UART 1 UART 0x40102000 0x0 0x4C registers n UARTINTR1 UART1 interrupt 50 UARTCR Control register 0x30 read-write n 0x300 0xFFFFFFFF CTSEn CTS hardware flow control enable 15 1 Disable CTS hardware flow control is disabled 0 Enable CTS hardware flow control is enabled 1 DTR Data transmit ready 10 1 LBE Loop back enable 7 1 Disable Loop back mode is disabled 0 Enable Loop back mode is enabled 1 Out1 Complement of the UART Out1 12 1 Out2 Complement of the UART Out2 13 1 RTS Request to send 11 1 RTSEn RTS hardware flow control enable 14 1 Disable RTS hardware flow control is disabled 0 Enable RTS hardware flow control is enabled 1 RXE Receive enable 9 1 Disable Reception is disabled 0 Enable Reception is enabled 1 SIREN SIR enable 1 1 Disable SIR is disabled 0 Enable SIR is enabled 1 SIRLP IrDA SIR low power mode 2 1 Disable SIR low power mode is disabled 0 Enable SIR low power mode is enabled 1 TXE Transmit enable 8 1 Disable Transmission is disabled. 0 Enable Transmission is enabled. 1 UARTEN UART enable 0 1 Disable UART is disabled 0 Enable UART is enabled 1 UARTDMACR DMA control register 0x48 read-write n 0x0 0xFFFFFFFF DMAONERR DMA on error 2 1 Disable DMA receive request outputs are enabled when the UART error interrupt is asserted 0 Enable DMA receive request outputs are disabled when the UART error interrupt is asserted 1 RXDMAE Receive DMA enable 0 1 Disable Receive DMA is disabled 0 Enable Receive DMA is enabled 1 TXDMAE Transmit DMA enable 1 1 Disable Transmit DMA is disabled 0 Enable Transmit DMA is enabled 1 UARTDR Data register 0x0 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 10 1 Data Receive/Transmit data 0 8 FE Framing error: Indicates the received character did not had a valid stop bit 8 1 OE Overrun error: Indicates if data is received and the receive FIFO is already full. 11 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 9 1 UARTFBRD Fractional baud rate register 0x28 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 6 UARTIBRD Integer baud rate register 0x24 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 16 UARTICR Interrupt clear register 0x44 write-only n 0x0 0xFFFFFFFF BEIC Break error interrupt clear, write 1 to clear, write 0 has no effect 9 1 CTSMIC nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect 1 1 DCDMIC nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect 2 1 DSRIC nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect 3 1 FEIC Framing error interrupt clear, write 1 to clear, write 0 has no effect 7 1 OEIC Overrun error interrupt clear, write 1 to clear, write 0 has no effect 10 1 PEIC Parity error interrupt clear, write 1 to clear, write 0 has no effect 8 1 RIMIC nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect 0 1 RTIC Receive timeout interrupt clear, write 1 to clear, write 0 has no effect 6 1 RXIC Receive interrupt clear, write 1 to clear, write 0 has no effect 4 1 TXIC Transmit interrupt clear, write 1 to clear, write 0 has no effect 5 1 UARTIFLS Interrupt FIFO level select register 0x34 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive interrupt FIFO level select 3 3 1/8 full Receive FIFO becomes greater than or equal to 1/8 full 0 1/4 full Receive FIFO becomes greater than or equal to 1/4 full 1 1/2 full Receive FIFO becomes greater than or equal to 1/2 full 2 3/4 full Receive FIFO becomes greater than or equal to 3/4 full 3 7/8 full Receive FIFO becomes greater than or equal to 7/8 full 4 TXIFLSEL Transmit interrupt FIFO level select 0 3 1/8 full Transmit FIFO becomes less than or equal to 1/8 full 0 1/4 full Transmit FIFO becomes less than or equal to 1/4 full 1 1/2 full Transmit FIFO becomes less than or equal to 1/2 full 2 3/4 full Transmit FIFO becomes less than or equal to 3/4 full 3 7/8 full Transmit FIFO becomes less than or equal to 7/8 full 4 UARTILPR IrDA low-power counter register 0x20 read-write n 0x0 0xFFFFFFFF ILPDVSR 8-bit low-power divisor value 0 8 UARTIMSC Interrupt mask set/clear register 0x38 read-write n 0x0 0xFFFFFFFF BEIM Break error interrupt mask 9 1 Clear Clears the mask 0 Set Sets the mask 1 CTSMIM nUARTCTS modem interrupt mask. 1 1 Clear Clears the mask 0 Set Sets the mask 1 DCDMIM nUARTDCD modem interrupt mask 2 1 Clear Clears the mask 0 Set Sets the mask 1 DSRMIM nUARTDSR modem interrupt mask 3 1 Clear Clears the mask 0 Set Sets the mask 1 FEIM Framing error interrupt mask 7 1 Clear Clears the mask 0 Set Sets the mask 1 OEIM Overrun error interrupt mask 10 1 Clear Clears the mask 0 Set Sets the mask 1 PEIM Parity error interrupt mask 8 1 Clear Clears the mask 0 Set Sets the mask 1 RIMIM nUARTRI modem interrupt mask 0 1 Clear Clears the mask 0 Set Sets the mask 1 RTIM Receive timeout interrupt mask 6 1 Clear Clears the mask 0 Set Sets the mask 1 RXIM Receive interrupt mask 4 1 Clear Clears the mask 0 Set Sets the mask 1 TXIM Transmit interrupt mask 5 1 Clear Clears the mask 0 Set Sets the mask 1 UARTLCR_H Line control register 0x2C read-write n 0x0 0xFFFFFFFF BRK Send break 0 1 EPS Even parity select 2 1 FEN Enable FIFOs 4 1 PEN Parity enable 1 1 SPS Stick parity select 7 1 STP2 Two stop bits select 3 1 WLEN Word length 5 2 UARTMIS Masked interrupt status register 0x40 read-only n 0x0 0xFFFFFFFF BEMIS Break error masked interrupt status 9 1 CTSMMIS nUARTCTS modem masked interrupt status. 1 1 DCDMMIS nUARTDCD modem masked interrupt status 2 1 DSRMMIS nUARTDSR modem masked interrupt status 3 1 FEMIS Framing error masked interrupt status 7 1 OEMIS Overrun error masked interrupt status 10 1 PEMIS Parity error masked interrupt status 8 1 RIMMIS nUARTRI modem masked interrupt status 0 1 RTMIS Receive timeout masked interrupt status 6 1 RXMIS Receive masked interrupt status 4 1 TXMIS Transmit masked interrupt status 5 1 UARTRFR Flag register 0x18 read-only n 0x0 0xFFFFFFFF BUSY UART busy 3 1 CTS Clear to send 0 1 DCD Data carrier detect 2 1 DSR Data set ready 1 1 RI Ring indicator 8 1 RXFE Receive FIFO empty 4 1 RXFF Receive FIFO full 6 1 TXFE Transmit FIFO empty 7 1 TXFF Transmit FIFO full 5 1 UARTRIS Raw interrupt status register 0x3C read-only n 0x0 0xFFFFFFFF BERIS Break error interrupt status 9 1 CTSRMIS nUARTCTS modem interrupt status. 1 1 DCDRMIS nUARTDCD modem interrupt status 2 1 DSRRMIS nUARTDSR modem interrupt status 3 1 FERIS Framing error interrupt status 7 1 OERIS Overrun error interrupt status 10 1 PERIS Parity error interrupt status 8 1 RIRMIS nUARTRI modem interrupt status 0 1 RTRIS Receive timeout interrupt status 6 1 RXRIS Receive interrupt status 4 1 TXRIS Transmit interrupt status 5 1 UARTRSR_UARTECR Receive status register/error clear register 0x4 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 2 1 FE Framing error: Indicates the received character did not had a valid stop bit 0 1 OE Overrunerror: Indicates if data is received and the receive FIFO is already full. 3 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 1 1 UART1_Secure UART 1 (Secure) FLC 0x50102000 0x0 0x1000 registers n BL_CTRL Bootloader Control Register 0x170 read-write n 0x0 0xFFFFFFFF BYPASS Status Flags for DSB Operations 0x9C read-write n 0x0 0xFFFFFFFF destruct_bypass_complete Destructive Security Bypass Erase Complete 2 3 read-only destruct_bypass_erase Destructive Security Bypass In Progress 0 1 read-only superwipe_complete Superwipe Erase Complete 3 4 read-only superwipe_erase Superwipe Erase In Progress 1 2 read-only CTRL Flash Control Register 0x8 read-write n 0x0 0xFFFFFFFF auto_incre_mode Address Auto-Increment Mode 27 28 read-write erase_code Flash Erase Code 8 16 read-write flsh_unlock Flash Write/Erase Enable 28 32 read-write info_block_unlock Flash Info Block Locked 16 17 read-only info_block_valid Info Block Valid Status 25 26 read-only mass_erase Start Flash Mass Erase Operation 1 2 read-write page_erase Start Flash Page Erase Operation 2 3 read-write pending Flash Controller Status 24 25 read-only write Start Flash Write Operation 0 1 read-write write_enable Flash Writes Enabled 17 18 read-only CTRL2 Flash Control Register 2 0x140 read-write n 0x0 0xFFFFFFFF bypass_ahb_fail AHB Fail Bypass 8 16 read-write flash_lve Flash LVE Enable 0 8 read-write DISABLE_WE0 Disable Flash Page Write/Erase Register 0 0x300 read-write n 0x0 0xFFFFFFFF DISABLE_WE1 Disable Flash Page Write/Erase Register 1 0x304 read-write n 0x0 0xFFFFFFFF DISABLE_WE2 Disable Flash Page Write/Erase Register 2 0x308 read-write n 0x0 0xFFFFFFFF DISABLE_WE3 Disable Flash Page Write/Erase Register 3 0x30C read-write n 0x0 0xFFFFFFFF DISABLE_WE4 Disable Flash Page Write/Erase Register 4 0x310 read-write n 0x0 0xFFFFFFFF DISABLE_WE5 Disable Flash Page Write/Erase Register 5 0x314 read-write n 0x0 0xFFFFFFFF DISABLE_WE6 Disable Flash Page Write/Erase Register 6 0x318 read-write n 0x0 0xFFFFFFFF DISABLE_WE7 Disable Flash Page Write/Erase Register 7 0x31C read-write n 0x0 0xFFFFFFFF DISABLE_XR0 Disable Flash Page Exec/Read Register 0 0x200 read-write n 0x0 0xFFFFFFFF DISABLE_XR1 Disable Flash Page Exec/Read Register 1 0x204 read-write n 0x0 0xFFFFFFFF DISABLE_XR2 Disable Flash Page Exec/Read Register 2 0x208 read-write n 0x0 0xFFFFFFFF DISABLE_XR3 Disable Flash Page Exec/Read Register 3 0x20C read-write n 0x0 0xFFFFFFFF DISABLE_XR4 Disable Flash Page Exec/Read Register 4 0x210 read-write n 0x0 0xFFFFFFFF DISABLE_XR5 Disable Flash Page Exec/Read Register 5 0x214 read-write n 0x0 0xFFFFFFFF DISABLE_XR6 Disable Flash Page Exec/Read Register 6 0x218 read-write n 0x0 0xFFFFFFFF DISABLE_XR7 Disable Flash Page Exec/Read Register 7 0x21C read-write n 0x0 0xFFFFFFFF FADDR Flash Operation Address 0x0 read-write n 0x0 0xFFFFFFFF faddr Flash Operation Address 0 22 read-write FCKDIV Flash Clock Pulse Divisor 0x4 read-write n 0x0 0xFFFFFFFF auto_fckdiv_result Auto FCKDIV Calculation Result 16 32 read-only fckdiv Flash Clock Pulse Divisor 0 7 read-write FDATA Flash Operation Data Register 0x30 read-write n 0x0 0xFFFFFFFF INTEN1 Interrupt Enable/Disable Register 1 0x148 read-write n 0x0 0xFFFFFFFF flash_read_locked Flash Read from Locked Area Interrupt Enable/Disable 2 3 read-write oneToClear flc_prog_complete Program (Write or Erase) Op Completed Int Enable/Disable 5 6 read-write flc_state_done FLC State Machine Reached DONE Interrupt Enable/Disable 4 5 read-write invalid_flash_addr Invalid Flash Address Interrupt Enable/Disable 1 2 read-write oneToClear sram_addr_wrapped SRAM Address Wrapped Interrupt Enable/Disable 0 1 read-write oneToClear trim_update_done Trim Update Complete Interrupt Enable/Disable 3 4 read-write oneToClear INTFL1 Interrupt Flags Register 1 0x144 read-write n 0x0 0xFFFFFFFF flash_read_locked Flash Read from Locked Area Interrupt Flag 2 3 read-write oneToClear flc_prog_complete Program (Write or Erase) Operation Completed Interrupt Flag 5 6 read-write oneToClear flc_state_done FLC State Machine Reached DONE Interrupt Flag 4 5 read-write oneToClear invalid_flash_addr Invalid Flash Address Interrupt Flag 1 2 read-write oneToClear sram_addr_wrapped SRAM Address Wrapped Interrupt Flag 0 1 read-write oneToClear trim_update_done Trim Update Complete Interrupt Flag 3 4 read-write oneToClear INTR Flash Controller Interrupt Flags and Enable/Disable 0 0x24 read-write n 0x0 0xFFFFFFFF failed_ie Flash Operation Failed Interrupt Enable 9 10 read-write failed_if Flash Operation Failed 1 2 read-write fail_flags Flash Operation Failure Details 16 32 read-only finished_ie Flash Write/Erase Operation Finished Interrupt Enable 8 9 read-write finished_if Flash Write/Erase Operation Finished 0 1 read-write PDM33 PDM33 Register 0x178 read-write n 0x0 0xFFFFFFFF PERFORM Flash Performance Settings 0x50 read-write n 0x0 0xFFFFFFFF auto_clkdiv Auto CLKDIV 29 30 read-write auto_tacc Auto TACC 28 29 read-write delay_se_en Delay SE Enable (Deprecated) 0 1 read-write en_back2back_rds Enable Back To Back Reads 16 17 read-write en_back2back_wrs Enable Back To Back Writes 20 21 read-write en_merge_grab_gnt Enable Merge Grab GNT 24 25 read-write en_prevent_fail Prevent Fail Flag Set on FLC Busy 12 13 read-write fast_read_mode_en Fast Read Mode Enable (Deprecated) 8 9 read-write SECURITY Flash Controller Security Settings 0x88 read-write n 0x0 0xFFFFFFFF debug_disable Debug Lockout 0 8 read-write disable_ahb_wr Disable AHB Flash Write Operations 16 20 read-write flc_settings_lock FLC Settings Lock 24 28 read-write mass_erase_lock Mass Erase Lockout 8 12 read-write security_lock Security Lock 28 32 read-write SLM Sleep Mode Register 0x17C read-write n 0x0 0xFFFFFFFF STATUS Security Status Flags 0x80 read-write n 0x0 0xFFFFFFFF auto_lock Debug Locked - Auto Lock 3 4 read-only info_block_valid Info Block Valid 30 31 read-only jtag_lock_static Debug Locked - Firmware Lockout 1 2 read-only jtag_lock_window Debug Locked - Hardware Window 0 1 read-only trim_update_done Trim Update Done 29 30 read-only TACC Flash Read Cycle Config 0x54 read-write n 0x0 0xFFFFFFFF TPROG Flash Write Cycle Config 0x58 read-write n 0x0 0xFFFFFFFF TWK_CYCL_CNT Cycle Count Tweak Register 0x174 read-write n 0x0 0xFFFFFFFF USER_OPTION Used to set DSB Access code and Auto-Lock in info block 0x100 read-write n 0x0 0xFFFFFFFF WATCHDOG Non-secure Watchdog Timer WATCHDOG 0x40081000 0x0 0xC04 registers n NONSEC_WATCHDOG_IRQ Non-Secure Watchdog Interrupt 1 WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF WATCHDOG_Secure Watchdog (Secure) WATCHDOG 0x50081000 0x0 0xC04 registers n WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF